DMA-based ethernet packet acceleration for broadband wireless physical layer processing

As broadband wireless communication systems scale to support massive data rates and ultra-low latency requirements, data movement within physical layer (PHY) platforms has emerged as a critical bottleneck. Direct Memory Access (DMA)-based Ethernet packet acceleration has become a key enabler for high-speed, low-latency communication in 5G and beyond. This review provides a comprehensive analysis of architectural strategies, performance metrics, and integration techniques of DMA within wireless PHY systems. It highlights how DMA-based designs can improve throughput, reduce CPU load, and enhance real-time responsiveness in edge and cloud-based radio access networks. The review concludes by discussing open challenges and future research directions aimed at achieving scalable, secure, and energy-efficient DMA architectures for next-generation wireless systems.