Non-minimum phase compensation in quadratic boost converters using PID dual-loop strategies

This paper presents a dual-loop PID control strategy to address the non-minimum phase (NMP) challenge in Quadratic Boost Converters (QBC-B). The proposed architecture combines an inner current-control loop (PI) and an outer voltage-regulation loop (PID) to compensate for the right-half-plane zero inherent to QBC-B dynamics. Using averaged state-space modeling and frequency-domain analysis, we derive design criteria ensuring stability under bandwidth constraints imposed by the NMP characteristic. The controller is validated through high-fidelity simulations, demonstrating <2% steady-state error, 27.5% maximum voltage deviation during 50% load steps, and recovery times under 1.6 s. Key innovations include anti-windup integration and current-reference saturation to handle bilinear effects while maintaining CCM operation. Compared to single-loop alternatives, the dual-loop approach reduces overshoot to 0% in reference tracking and improves robustness against input variations (10 V-15 V). The work provides practical tuning guidelines for power electronics engineers dealing with high-gain converters where NMP behavior limits conventional PID designs.