CTS-Aware Voltage Scaling Across Distributed Corners: A New Approach to Clock Robustness in Sub-5nm SoCs

The aspect of providing consistently low-energy clock distribution in sub-5nm space has been of high priority, as the processes in which power and requirements have changed with the advent of System-on-Chip (SoC) applications. Conventional methods of scaling voltage without taking into account Clock Tree Synthesis (CTS) are likely to result in timing failures and poor power usage. The current paper presents a discourse on the novel paradigm of CTS-conscious voltage scaling, in which voltage management is tightly combined with clock synthesis and clock allocation policies to provide robustness at the boundaries of distributed processes. It is supported by shift-left methodologies, FinFET-based CMOS technology innovations, scalable silicon architectures, and device-level innovations, including junctionless FishBone FETs. It introduces CTS-conscious voltage scaling as an enabling core service of low-power, high-performance SoCs in advanced nodes by investigating its performance, area, variability, and clock signal integrity consequences.